TOKYO — In a major boost for silicon-on-insulator technology, Toshiba Corp. will adopt Canon Inc.'s Eltran SOI wafer process for broadband microprocessors built in 0.1-micron and 0.07-micron process ...
Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during ...
As a partner of Taiwan Semiconductor Manufacturing Co. (TSMC), Altera Corp. today announced it has achieved two milestones in 0.13-micron and 300mm technology. Programmable logic supplier Altera ...
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The Chinese module maker and the Australian National University utilized phosphorus diffusion gettering and another defect mitigation strategy to improve the quality of n-type wafers. The proposed ...
Hongyuan Green Energy says it has produced a first batch of 40 µm monocrystalline silicon wafers that support full-size and half-cut formats, with slicing completed using the company’s in-house ...
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