Design-Reuse

Synopsys Integrates VERA and VCS to Boost Verification Performance

VCS Direct Kernel Interface, Coverage Engine Integration and Waveform Analysis Integration Raise Verification Performance and Productivity MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Nov. 12, 2001-- ...
Electronic Design

Verilog Simulator Adds Full-Featured Coverage Analysis And A C/C++ Interface

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
Semiconductor Engineering

Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics

Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Semiconductor Engineering

Intelligent Coverage Optimization: Verification Closure In Hyperdrive

Coverage dominates every aspect of verification for today’s complex IP and chip designs. Coverage metrics provide critical feedback on what has been verified and what has not, especially when ...