We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based ...
CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software to be available through Intel Pathfinder for RISC-V ROCKVILLE, Md., Dec. 1, 2022 /PRNewswire/ -- CEVA, Inc. (NASDAQ: CEVA), the leading ...
CHIPS Alliance has developed an open-source riscv-dv random instruction generator for RISC-V processor verification. This article focuses on the class riscv_asm_program_gen.sv and its various ...
It’s pretty neat to flash firmware on a microcontroller thousands of miles away and see the development board blink in response. We’ve covered the Open-V before, and the crowd funding campaign they ...
This program is a new way for embedded system developers to adopt RISC-V processors faster and with less risk. Catalyst combines CAST’s 32-bit RISC-V processor IP cores with simplified configurations, ...
Early access program starts for PolarFire SoC, which delivers simultaneous support of real-time applications and rich operating systems with unparalleled power efficiency CHANDLER, Ariz., Dec. 10, ...
The open-source nature of RISC-V brings the benefits of a modular and royalty-free instruction set architecture (ISA) that eliminates licensing fees, can accelerate development, and fosters ...
READING, United Kingdom, May 28, 2025 — Aion Silicon (formerly Sondrel), an ASIC and SoC architecture partner, today announced it has secured a $12 million engagement to provide design services for a ...
Targeted, preconfigured RISC-V IP cores plus low-risk, easy-start, deferred-payment IP licensing make embedded RISC-V design easier than ever Santa Clara, California, RISC-V Summit — October 22, 2025 ...
V – Open Architecture for Embedded, AI, and Automotive” is only valid until March 20th. The early bird discount for the ...
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