As technology nodes shrink to 90 nanometers and below, chips become much more difficult to manufacture. In-die process variations increase substantially at 90 nm — even more at 65 nm. If these effects ...

Venice, Florida &@8212 Solido Design Automation has introduced a scalable and extensible solution for meeting design challenges created by process variations at nanometer feature sizes. The new ...

Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from ...

With semiconductor feature sizes continuing to shrink, the variability arising from process technologies such as strained silicon, as well as the manufacturing processes themselves at 45 nm and below, ...

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and ...