EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.
Semiconductor Engineering

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.
Nature

Cache Management and Partitioning in Multicore Systems

Modern multicore systems demand sophisticated strategies to manage shared cache resources. As multiple cores execute diverse workloads concurrently, cache interference can lead to significant ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
PC World

How does CPU memory cache work?

In the eighties, computer processors became faster and faster, while memory access times stagnated and hindered additional performance increases. Something had to be done to speed up memory access and ...